Electronic integrated circuits (ICs) are usually exhaustively tested after their manufacture to assure that they perform according to their design. Because the fabrication of integrated circuits is so complex and requires precise dimensional controls, ICs are prone to defects introduced during their manufacture, and these defects can often affect only very few of the circuit elements, which can number in the millions. In complex ICs, the defective circuit element may be exposed in only one of a large number of test patterns that electrical test equipment imposes on the IC to determine whether the IC is correctly operating. Hence, elaborate high-speed automatic test equipment (ATE) has been developed for testing ICs.
Automatic testing and the associated ATE are usually divided into two distinct types. Memory testers test memory chips which contain a large number of memory cells arranged in regular arrays and additionally contain smaller amounts of support and interface circuitry. Generally, if each memory cell is tested in turn, then there is a high probability that the testing has uncovered every defect on the memory chip. Although it is common to test for different geometrically dependent fault patterns, e.g., all ones or a zero surrounded by ones, these patterns also can be shifted through the regularly arranged memory cells. As a result, for memory testing, the test patterns are relatively simple and the number of test sequences is proportional to N.sub.M, where N.sub.M is the number of memory cells.
In contrast to memory testers, logic testers test logic chips, such as microprocessors, controllers, and other related circuitry embodied in an integrated circuit. In general, complex logic has circuitry which requires several clock cycles to ingest particular sets of input data that exercise deeply embedded parts of the logic circuitry. The number of exhaustive test cycles may be much greater than N.sub.L, the number of logic gates on the chip. Also, advanced logic circuitry may have several hundred input and output pins. Logic testing therefore requires well considered test vectors applied to testers with large number of input probes and output probes.
The result is that commercial ATE equipment has developed along two paths. One type of equipment includes memory testers, the other type includes VLSI (very large-scale integrated-circuit) testers for testing logic circuitry, and the use of one type of tester to test the other type of circuitry at a minimum introduces severe inefficiencies. An example of a commercial VLSI tester is the Duo from Credence, Inc. of Beaverton, Oreg.
Modern video controllers have an integrated-circuit structure that does not neatly fit the above division of integrated circuits and associated test equipment. A video controller is used, for example, in personal computers to receive video control signals from the microprocessor and to translate those signals into a continuous stream of usually analog signals to control a cathode ray tube (CRT) or other equivalent display. Video controllers have become increasingly important with the advent of graphical user interfaces and high-resolution displays, both of which place heavy demands on their video controllers. An example of a video controller integrated circuit, often called a video accelerator chip, is the CL-GD5434, available from Cirrus Logic, Inc. of Fremont, Calif. and which is described in the data book Alpine VGA Family--CL-GD543X: Technical Reference Manual, 3rd ed., 1994, available from Cirrus. This chip has 208 pins.
A very high-level circuit diagram of the above noted video controller and its electronic environment is shown in FIG. 1. A host computer 10, usually in the form of a motherboard including a microprocessor, is typically connected via a computer bus, such as a PCI bus 12, to a video controller board, such as a VGA board 14. It is, however, understood that the invention is not limited to VGA boards or PCI buses, which may be superseded by more advanced video boards and buses; and furthermore, the invention is not even limited to video boards or video controllers.
Although in the past the VGA board 14 was a printed circuit board including many different components, more recent video controllers have incorporated most of the functions onto a single video controller integrated circuit mounted on the board 14. In particular, large blocks of memory may be included on the same chip as the logic circuitry for the video controller, that is, memory is embedded in the logic chip. Video accelerator chip 16 is representative of such a video controller (also referred to as a VGA chip). Since so many functions have been integrated into the video accelerator chip 16, some designs place it and the relatively few other components needed for video controls on the computer motherboard of the host computer 10.
The PCI bus 12 may directly communicate with a logic section 18 of the video accelerator chip 16. The logic section 18 generally controls a video buffer 20 including a video first-in/first-out buffer section 22 and a cursor register 24, both of which input to a palette table 26 which converts the video and cursor signals to digital color signals of preselected colors on three digital color output lines 28. The palette table 26 is usually implemented as a static random-access memory (SRAM) of fairly small size, for example, principally a 256.times.18 section on the CL-GD543X operating as a look-up table. Although the described embodiment utilizes a 256.times.18 SRAM, it is anticipated that in more advanced video accelerator chips, the length of the words in the palette table will lengthen to N bits, requring a 256.times.N SRAM. The palette table 26 outputs, in one mode, 6 bits to each of the three digital color output lines 28 for any of 256 colors. A digital-to-analog converter 30 converts the digital color signals to three equivalent analog color signals R, G, B controlling the color display on an analog display 31, such as a cathode-ray tube (CRT). A CRT controller 34 outputs synchronization signals to the analog display 32 and also controls the cursor register 24.
The logic section 18 relies upon a large display memory 32, usually implemented in dynamic random-access memory (DRAM). In advanced video accelerator chips, the display DRAM is embedded in the chip 16. That is, the single IC video chip 16 includes both a large logic section and a large DRAM section. The DRAM 32 in present advanced video accelerator chips commonly has a size in the range of 1/2 to 2 megabytes. The large display memory 32 allows a relatively low flow of information on the PCI bus 12 to update a large amount of slowly changing color data in the display memory 32, thereby off loading display functions from the host computer 10. A more complete diagram of the accelerator chip 16 is provided on page 3-32 of the cited Cirrus reference manual.
A clock oscillator 34 on the video board 14 controls a frequency synthesizer 36 on the video accelerator chip 16, which produces at least two clocking signals for various components on the VGA chip. The separate timing circuitry can be used because the timing of the display 31 is fairly independent of the PCI bus 12. The video board 14 may also contain passive elements, such as for power conditioning. Similar types of video-control circuitry are generally required for non-CRT displays.
The SRAM 26 and DRAM 32 have significantly different characteristics. Static RAM is based on flip-flop circuitry that holds values in its memory as long as power to the SRAM is not removed. The SRAM 26 is relatively small and contains color-conversion information that changes only infrequently. It needs to be very fast to keep up with the video display rate, but SRAM tends to be relatively expensive and may consume substantial power. On the other hand, dynamic RAM is based on capacitive cells in a MOS circuits. These cells are inherently leaky, and their contents need to be refreshed periodically on the order of milliseconds. However, DRAM storage cells are small and simple compared to SRAM memory cells. As a result, the DRAM 32 can be made large but relatively inexpensive on a per-bit basis. Its speed is somewhat low but can be enhanced by block transfers which are characteristic of video mapping.
Manufacturers of video accelerator chips or of video boards must assure that their circuitry is operating correctly. However, the large embedded DRAM 32 of FIG. 1 presents a testing problem. A VLSI tester can fairly easily test the logic section 16 and the relatively small palette table SRAM 26 as well as other lesser circuitry. But testing the large DRAM 32 with a VLSI tester, particularly when it needs to interface through logic optimally designed for non-testing functions, becomes prohibitively long and expensive. The same constraints do not apply to testing the SRAM 26 since it is relatively small, for example, 256.times.18, so that a relatively few test vectors from the VLSI tester can test all the locations.
A memory tester is needed for testing the large DRAM 32. However, since the DRAM 32 is embedded in the video accelerator chip 16, additional input and output pins may be required on the packaged chip 16 to effectively access the DRAM for testing. Unfortunately, the number of pin-outs on video accelerator chips is already excessively high, and it is desired to not provide extra pin-outs for memory testing. Furthermore, using two different types of testers, a VLSI tester for the logic portion and a memory tester for the DRAM portion, requires two types of expensive equipment and lengthens the testing operation.
Accordingly, it is desired to provide a method of testing DRAM embedded on a board or in a chip by a VLSI tester.
The testing of embedded RAM is an old problem One solution involving built-in self test (BIST) is described by Fasang et al. in U.S. Pat. No. 5,138,619, issued Aug. 11, 1992 and entitled BUILT-IN SELF TEST FOR INTEGRATED CIRCUIT MEMORY. However, this approach to BIST relies on pseudo-random program generators for producing the address and data used in the testing, and provides a relatively rigid test regimen.